The present invention relates to a method for manufacturing a thin film transistor (TFT) panel for a liquid crystal display (LCD) by photolithography and a photolithography method for fabricating thin films, especially to a method to reduce the number of photolithography steps in manufacturing a TFT panel for an LCD.
An LCD (liquid crystal display) is one of the most popular FPDs (flat panel displays). The LCD has two panels having two kinds of electrodes for generating electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes may be formed at each of the panels, or at one of the panel. The panel having at least one kind of the electrodes has switching elements such as thin film transistors.
In general, a TFT (thin film transistor) array panel of an LCD includes a plurality of pixel electrodes and TFTs controlling the signals supplied to the pixel electrodes. The TFT array panel is manufactured by photolithography using a plurality of photomasks, and it goes through five or six photolithography steps to complete the TFT array panel. The high costs and long time that the photolithography process bears makes it desirable to reduce the number of the photolithography steps.
Several manufacturing methods of LCDs using only four photolithography steps are suggested such as in Korean Patent Application No. 1995-189 (""189). The corresponding U.S. patent is U.S. Pat. No. 5,818,551. In the meantime, since an LCD actually requires wires for transmitting electric signals to the TFTs and wire pads for receiving the signals from outside, the full process to complete a TFT array panel requires the step of forming the pads. However, ""189 does not disclose how to form the pads.
Other conventional method of manufacturing a TFT array panel using four photolithography steps is disclosed in xe2x80x9cA TFT Manufactured by 4 Masks Process with New Photolithography (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, pp. 1109-1112, 1998. 9.28-10.1).
Meanwhile, a storage capacitor for sustaining the voltage applied to a pixel is generally provided in the TFT array panel, and the storage capacitor includes a storage electrode and a portion of a pixel electrode as well as a passivation layer interposed therebetween. The storage electrode is made of the same layer as a gate wire, and the portion of the pixel electrode is formed on the passivation layer. The storage electrode is covered with a gate insulating layer, a semiconductor layer and a passivation layer, and most portion of the pixel electrode is formed directly on the substrate in Han et al., Therefore, the pixel electrode should step up the triple layers of the gate insulating layer, the semiconductor layer and the passivation layer, in order to overlap the storage electrode. It may cause a disconnection of the pixel electrode near the high step-up area.
In the meantime, as shown in ""189, the conventional photolithography process uses a photoresist (PR) layer. The conventional photoresist layer is exposed to light through a photomask and divided into two sections, one exposed to the light and the other not exposed. The development of the photoresist layer forms the PR pattern having a uniform thickness with the PR layer exposed to the light removed. Accordingly, the etched thickness of the layers under the PR pattern is also uniform. However, Han et al. uses a photomask having a grid, which lowers the amount of light reaching the portion of a positive PR layer thereunder, to form a PR pattern having thinner portions than the other portions. The different thickness of the PR pattern produces the different etching depth of the underlying layers.
Therefore, Han et al. has a problem in forming the grid throughout a wide region, and it is hard to make the etching depth uniform under the grid region, even though the grid is formed throughout the wide region.
U.S. Pat. Nos. 4,231,811, 5,618,643, and 4,415,262 and Japanese patent publication No. 61-181130, etc., which disclose similar methods as Han et al., have the same problem.
It is therefore an object of the present invention to suggest a novel method for manufacturing thin films using photolithography.
It is another object of the present invention to simplify the manufacturing method of a TFT array panel for an LCD, thereby reducing the manufacturing cost and increasing the productivity.
It is another object of the present invention to etch thin films to a different uniform depths depending on the position, at the same time.
These and other objects are provided, according to the present invention, by forming a contact hole for a gate pad along with at least one other layer.
According to the present invention, a gate wire including a plurality of gate lines, gate electrodes and gate pads, is formed on a substrate having a display area and a peripheral area. A gate insulating layer pattern is formed thereon. A semiconductor pattern is formed on the gate insulating layer, and a ohmic contact pattern is formed on the semiconductor pattern. Then, a data wire including data lines, source and drain electrodes located on the display area, and data pads located on the peripheral area is formed thereon. A passivation layer for channel is formed and a plurality of pixel electrodes connected to the drain electrodes are formed. At this time, the gate insulating layer pattern is formed along with at least one other layer through a photolithography process using a photoresist pattern of which thickness is varying according to location.
It is preferable that the photoresist pattern has a first portion located at the position corresponding to the gate pad, a second portion which is thicker than the first portion and located in the display area, and a third portion which is thicker than the second portion.
The photoresist pattern is formed on the passivation layer. The gate insulating layer pattern, the semiconductor layer pattern and the passivation layer pattern are formed by etching the passivation layer and the semiconductor layer under the first portion of the photoresist pattern, and the second portion of the photoresist pattern at the same time. Then, the second portion of the photoresist pattern to expose the passivation layer thereunder is removed by an ashing process, etching the passivation layer and the gate insulating layer to expose the semiconductor layer under the first portion and to form a first contact hole exposing the gate pad under the first portion by using the photoresist pattern as an etch mask, and removing the semiconductor layer under the second portion by using the photoresist pattern as an etch mask.
At this time, a second contact hole exposing the data pad may be formed in the step of etching passivation layer and the semiconductor layer under the first portion or forming the first contact hole. A third contact hole exposing the drain electrode may be formed in the step of forming the first contact hole or etching the passivation layer and the semiconductor layer under the first portion. The etching step of the passivation layer and the semiconductor layer may be performed by a dry etch of using SF6+O2 or SF6+HCl as an etch gas, and the ashing process may be performed by using N2+O2 or O2+Ar gas. The semiconductor layer may be made of amorphous silicon, and the first contact hole may be formed by using one of such gases as SF6+O2, SF6+N2, CF4+O2 and CF4+CHF3+O2, which have a high etch selectivity between the passivation layer and the semiconductor layer. The semiconductor layer may be removed by a dry etch using Cl6+O2 or SF6+HCl+Ar+O2 as an etch gas. A redundant gate pad and a redundant data pad respectively covering the gate pad and the data pad is formed while forming the pixel electrode.
A gate wire, including gate lines, gate electrodes and gate pads, is formed on a substrate. A gate insulating layer pattern covering the gate wire except for at least a part of the gate pad, a semiconductor layer pattern, a ohmic contact layer pattern are formed on the gate wire. A data wire, including data lines, source and drain electrodes and data pads, is formed on the ohmic contact layer pattern. A passivation layer pattern and pixel electrodes are formed thereon. At this time, the gate insulating layer pattern is formed along with at least one of such patterns as the semiconductor pattern, the ohmic contact layer pattern, the data wire, the passivation layer pattern and the pixel electrode through a photolithography process. The photolithography process comprises the steps of coating a photoresist layer, exposing the photoresist layer through a photomask having a first part, a second part and a third part of which transmittance are different from each other and developing the photoresist layer to form a photoresist pattern. The exposing step may be done by using two kinds of photomask. The first photomask has a first part and a second part having a higher transmittance than that of the first part, and the second photomask has a third part of which transmittance is higher than that of the first part but lower than that of the second part and a fourth part of which transmittance is the same as that of the first part. At this time, the transmittance of the second part of the photomask is 20% to 60% of that of the first part and the transmittance of the third part is lower than 3%. The photomask having a substrate and at least one mask layer, and the difference of transmittance between the first part and the second part is made by using materials having different transmittance or differentiating the thickness of the mask layer. The difference of transmittance may be made by forming slits or a grid pattern smaller than the resolution of the stepper.
According to the present invention, a new photolithography method of thin films is provided.
In concrete, at least a thin film is formed on a substrate and a photoresist layer is coated on the thin film. The photoresist layer is exposed to a light through at least a photomask having more than three part of which transmittance are different from each other, and developed to form a photoresist pattern of which thickness is varying according to the location. The thin film is etched along with the photoresist pattern.
A dry etching method and the positive photoresist layer are preferred.
At least a thin film is formed on a substrate, and a photoresist pattern which has a first portion, a second portion of which thickness is thicker than that of the first portion and a third portion of which thickness is thicker than that of the second portion is formed on the thin film. The portion of the thin film under the first portion is etched along with the first portion but the second and the third portion protect the portions of the thin film under them. The photoresist pattern is stripped to expose the thin film under the second portion but leave the third portion to a certain thickness. The exposed portion of the thin film is etched but the third portion protects the portion of the thin film thereunder.
It is preferable that the stripping step of photoresist pattern is performed by an ashing process.
Another manufacturing method of a thin film transistor array panel is provided.
In concrete, a gate wire including a plurality of gate lines, gate electrodes and gate pads is formed on an insulating substrate. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited on the gate wire. The conductor layer and the ohmic contact layer is patterned by photolithography to form a data wire including a plurality of data lines, source electrodes, drain electrodes and data pads, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a photoresist layer is coated on the passivation layer. A photoresist pattern of which thickness is varying according to the location is formed by exposure and development. The passivation layer, the semiconductor layer and the gate insulating layer are etched along with the photoresist pattern to form a passivation layer pattern, a semiconductor layer pattern, and a gate insulating layer pattern having contact holes exposing the gate pads and a none-zero thickness in the display area, and a plurality of pixel electrodes respectively connected to the drain electrodes is formed on the passivation layer.
At this time, a plurality of redundant gate pads and redundant data pads respectively covering the gate pads and the data pads may be formed in the forming step of the pixel electrodes.
A first metal layer is deposited on a substrate and a gate wire including a plurality of gate lines and gate pads is formed by a first photolithography process. A first insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer is deposited on the gate wire. The second metal layer and the ohmic contact layer are patterned to form a data wire including a plurality of data lines, data pads, source electrodes and drain electrodes, and an ohmic contact layer pattern thereunder by a second photolithography process. A second insulating layer is deposited. The second insulating layer, the semiconductor layer and the first insulating layer is patterned to form a passivation layer pattern that covers the gate wire, the data wire and the portions of the semiconductor between the source electrode and the drain electrode and exposes a portion of the drain electrodes and the data pads, a semiconductor layer pattern having separated portion at least on the gate wire, and a gate insulating layer pattern exposing the gate pad by a third photolithography process. A transparent conductor layer is deposited and patterned to form a plurality of pixel electrodes connected to the drain electrode, redundant gate pads and redundant data pads respectively covering the gate pads and the data pads.
At this time, the third photolithography process may comprise the steps of coating a photoresist layer on the second insulating layer and exposing the photoresist layer by using a photomask having at least two portions, of which transmittance are different from each other. The third photolithography process may comprise a development step after the exposure to form a photoresist pattern having at least three different heights. The third photolithography process may comprise etching step of the photoresist pattern, the second insulating layer, the semiconductor layer and the first insulating layer to remove the first portion which is the lowest portion, and the second insulating layer, the semiconductor layer and the first insulating layer thereunder to expose the gate pads, and to remove the second portion which is higher than the first portion, and the second insulating layer and the semiconductor layer thereunder, but not remove the second insulating layer under the third portion which is higher than the second portion. The etching step of the photoresist pattern, the second insulating layer, the semiconductor layer and the first insulating layer comprises the steps of etching the second insulating layer, the semiconductor layer and the first insulating layer under the first portion of the photoresist pattern by using the second and the third portion as an etch stopper, removing the second portion of the photoresist layer to expose the second insulating layer thereunder by ashing process, and etching the exposed portion of the second insulating layer and the semiconductor layer thereunder by using the third portion of the photoresist layer as an etch stopper. The ashing process is performed by using oxygen. The transmittance difference of the photomask may be controlled by differentiating the thickness of a mask layer. The photomask may be classified into a first mask for the gate pad and a second mask for elsewhere, and the transmittance of the first mask is different from that of the second mask. The pixel electrodes may be formed just on the first insulating layer extended from under the data wire or under the drain electrode. The semiconductor layer may be made of amorphous silicon. The ohmic contact layer may be made of amorphous silicon doped with phosphorus. The transparent conductor layer may be made of indium-tin-oxide.
A TFT array panel having structure as following is manufactured by the method described above.
A gate wire including a plurality of gate lines, gate electrodes and gate pads is formed on a insulating substrate, and a gate insulating layer having contact holes exposing the gate pads is formed on the gate wire. A semiconductor layer pattern is formed on the gate insulating layer, and an ohmic contact layer pattern is formed on the semiconductor layer pattern. A data wire having a layout substantially the same as that of the ohmic contact layer pattern and including a plurality of source electrodes, drain electrodes, data lines and data pads is formed on the ohmic contact layer pattern. A passivation layer pattern having contact holes exposing the gate pad, the data pad and the drain electrode and having a layout substantially the same as that of the semiconductor layer pattern except for the portions of the drain electrode and the data pad is formed on the data wire and has wider layout. A transparent electrode layer pattern is electrically connected to the exposed gate pad, data pad and drain electrode.
At this time, at least one portion of the transparent electrode pattern may contact with the gate insulation layer extending from under the drain electrode. A portion of the semiconductor layer pattern and the ohmic contact layer pattern may be formed on the gate line, a storage electrode may be formed on the ohmic contact layer pattern located on the gate line, and the storage electrode may be electrically connected to the transparent electrode pattern. The shape of the gate insulating layer may be different from that of the passivation layer pattern in a part where the transparent electrode pattern is formed.